名稱：DAC芯片AD5689控制代碼SPI接口（代碼在文末付費(fèi)下載）

軟件：QuartusII

語(yǔ)言：VHDL

代碼功能：

控制DAC芯片AD5689，通過(guò)芯片的SPI接口，進(jìn)行命令和地址、數(shù)據(jù)寫(xiě)入，控制DAC輸出模擬信號(hào)。

AD5689/AD5687采用多功能SPI接口，時(shí)鐘速率高達(dá)50 MHz，并均包含一個(gè)為1.8 V/3 V/5 V邏輯電平準(zhǔn)備的VLOGIC引腳。

設(shè)計(jì)語(yǔ)言使用VHDL，本代碼簡(jiǎn)單易懂，注釋詳細(xì)，可以方便改寫(xiě)為verilog代碼。

演示視頻：

FPGA代碼Verilog/VHDL代碼資源下載網(wǎng)：www.hdlcode.com

部分代碼展示

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
ENTITY?AD5689_driver?IS
???PORT?(
??????clock????:?IN?STD_LOGIC;--50MHz
??????SYNC_N???:?OUT?STD_LOGIC;--AD5689接口
??????AD_SDO???:?IN?STD_LOGIC;--AD5689接口
??????AD_SCK???:?OUT?STD_LOGIC;--AD5689接口
??????AD_SDI???:?OUT?STD_LOGIC;--AD5689接口
??????WR_data??:?IN?STD_LOGIC_VECTOR(15?DOWNTO?0)--輸入數(shù)字信號(hào)
???);
END?AD5689_driver;
ARCHITECTURE?trans?OF?AD5689_driver?IS
???constant???CMD??????:?STD_LOGIC_VECTOR(3?DOWNTO?0)?:=?"0011";--寫(xiě)指令
???constant???ADDRA????:?STD_LOGIC_VECTOR(3?DOWNTO?0)?:=?"0001";--通道A,通道B="1000",通道A和通道B="1001"
???
???SIGNAL?cnt?????????:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00000000";
???SIGNAL?AD_SCK_buf??:?STD_LOGIC?:=?'0';
???
???SIGNAL?WR_data_buf?:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0000000000000000";
???SIGNAL?AD_SDI_buf??:?STD_LOGIC?:=?'0';
BEGIN
???PROCESS?(clock)
???BEGIN
??????IF?(clock'EVENT?AND?clock?=?'1')?THEN
?????????IF?(cnt?>=?"00110101")?THEN--53
????????????cnt?<=?"00000000";
?????????ELSE
????????????cnt?<=?cnt?+?"00000001";--分頻計(jì)數(shù)器
?????????END?IF;
??????END?IF;
???END?PROCESS;
???
???PROCESS?(clock)
???BEGIN
??????IF?(clock'EVENT?AND?clock?=?'1')?THEN
?????????IF?(cnt?>=?"00000000"?AND?cnt?<=?"00000001")?THEN
????????????SYNC_N?<=?'1';--40ns之后,SYNC拉低，開(kāi)始進(jìn)入讀取數(shù)據(jù)的狀態(tài)
?????????ELSE
????????????SYNC_N?<=?'0';
?????????END?IF;
??????END?IF;
???END?PROCESS;
???
???PROCESS?(clock)
???BEGIN
??????IF?(clock'EVENT?AND?clock?=?'1')?THEN--clock2二分頻得到sck的值為--25MHz
?????????IF?(cnt?>?"00000001"?AND?cnt?<?"00110011")?THEN--1~51
????????????IF?(cnt(0)?=?'0')?THEN
???????????????AD_SCK_buf?<=?'0';?--cnt[0]==0的時(shí)候，sck為下降沿
????????????ELSE
???????????????AD_SCK_buf?<=?'1';--cnt[0]==1的時(shí)候，sck為上升沿

設(shè)計(jì)文檔：

1. 工程文件

1. 程序文件

1. 程序編譯

1. 仿真文件

1. 仿真圖

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